Field of the Invention
The invention relates in general to the improvement of the self-aligned silicide (Salicide) process, and more particularly to a process which combines the salicide process and a self-preamorphization process.
As the level of integration for MOS devices increases, resistance in the source/drain terminals of the MOS device gradually rises to a value comparable to the channel resistance of the MOS device. To ensure integrity at the shallow junction between metallic contacts and the MOS terminals, and for the downward adjustment of sheet resistance in the source/drain terminals, self-aligned silicide processes are now employed in the manufacturing of very large scale integrated (VLSI) and ultra large scale integrated (ULSI) circuits. However, the thermal stability of TiSi.sub.2 with narrow line is easily degraded by the thermal budget and TiSi.sub.2 thickness. Therefore, it is difficult to obtain a low sheet resistance and high uniformity Ti-salicide with narrow line (&lt;0.5 .mu.m). Pre-amorphization implantation has been reported to improved the resistance of TiS.sub.2. However, an additional implantation is needed for this technique, and cost is increased by this implantation.
One of the conventional methods to obtain a low sheet resistance comprises implanting arsenic (AS) or Argon (Ar) atoms into the surface of the amorphous silicon, and then performing a self-aligned silicide process, as shown in FIG. 1A-FIG. 1D.
First, as shown in FIG. 1A, a semiconductor substrate 10 is provided, and shallow trench isolation regions 12 and MOS transistors 10' are formed above the substrate 10. The MOS transistors 10' consisting of gate electrodes 18, spacers 16 formed around the periphery of the gate electrodes 18 and source/drain regions 14 formed near the surface of the substrate 10 and around the periphery of the gate electrodes 18. The spacers 16 can be made from material such as dielectric compound.
Next, in FIG. 1B, the surface of source/drain regions 14 are transformed into amorphous phase by implanting As or Ar atoms into the substrate 10 using gate electrodes 18 as masks. Thus, the thickness of the titanium metal formed in the subsequent process can be controlled and the resistance of the titanium silicide can be improved by this amorphous surface. However, this additional implantation step increases the cost of the process.
Next, referring to FIG. 1C, a layer of titanium metal 28 is deposited, for example, using magnetically controlled DC sputtering method, over the surface of the semiconductor substrate 10 to a thickness of about 200.about.1000.sub.--. Because the amorphous surface is pre-formed in the surface 24 of the source/drain regions 14, the titanium metal will not penetrate deeply into the source/drain regions 14, effectively controlling the resistance of the interface.
Next, in FIG. 1D, a layer of titanium silicide is formed at the interface between the titanium and silicon. Namely, a layer of titanium silicide 28a is formed on the surface of the source/drain regions 14 to reduce the sheet resistance of the source/drain regions 14. Meanwhile, a titanium silicide layer 28b is formed by using a rapid thermal process (RTP) which has two stages. The early titanium silicide is formed by using a rapid thermal anneal (RTA) with nitrogen gases at a temperature of about 600.degree..about.650.degree. C. in the first stage. Then, the unreacted titanium metal and the titanium nitride formed by the reaction between the titanium metal and nitrogen gases are removed, for example, by using a RCA cleaning solution. The RCA cleaning solution consists of NH.sub.4 OH/HDIW (Hot De-ionization Water)/H.sub.2 O.sub.2. The temperature is raised to about 800.degree.-900.degree. C. and the RTA process is performed with nitrogen gases to transfer the phase of the titanium silicide from C.sub.49 to C.sub.54 in the second stage. The titanium silicide is formed by the diffusion and chemical reaction between the titanium and silicon. Because of the low resistance of the titanium silicide, the ohmic contact formed at the interface between titanium and silicon will be excellent.
As the size of the device is diminished, a conventional pre-amorphous implantation process is performed to obtain a low sheet resistance and high uniformity titanium silicide with narrow line. However, this additional implantation step will increases the cost of the process.